blob: 24ea3cd3d8fb65f6c01877e76cfa92eb587b2a84 (
plain) (
blame)
1
2
3
|
Lark-based parser for Verilog netlists (structural Verilog without behavioral
statements). This is meant to be used to read netlists as generated by HDL logic
synthesizers such as Yosys.
|
