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Diffstat (limited to 'cad/verilog-mode.el/pkg-descr')
| -rw-r--r-- | cad/verilog-mode.el/pkg-descr | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/cad/verilog-mode.el/pkg-descr b/cad/verilog-mode.el/pkg-descr index 77062c89de70..3907b48a2258 100644 --- a/cad/verilog-mode.el/pkg-descr +++ b/cad/verilog-mode.el/pkg-descr @@ -5,5 +5,3 @@ greatly reduce Verilog coding time. Recent versions allow you to insert AUTOS in non-AUTO designs, so IP interconnect can be easily modified. You can also expand Verilog-2001 ".*" instantiations, to see what ports will be connected by simulators. - -WWW: https://www.veripool.org/wiki/verilog-mode |