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| author | Lexi Winter <ivy@FreeBSD.org> | 2025-12-01 03:19:41 +0000 |
|---|---|---|
| committer | Lexi Winter <ivy@FreeBSD.org> | 2025-12-01 03:19:41 +0000 |
| commit | 2e80774d0b20d167bc0a9e2b63dafbfb171c0d22 (patch) | |
| tree | 25f0138e1af8902b92dacc8cce09b267447c17db /cad/py-verilog-parser/pkg-descr | |
| parent | f85f2b2d6e5b7ed869376eb4b180c3a74a5c5da9 (diff) | |
| parent | 1a30da80670973368b399f2b01fe9c04b91a1273 (diff) | |
Merge remote-tracking branch 'freebsd/main' into lf/mainlf/main
Diffstat (limited to 'cad/py-verilog-parser/pkg-descr')
| -rw-r--r-- | cad/py-verilog-parser/pkg-descr | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/cad/py-verilog-parser/pkg-descr b/cad/py-verilog-parser/pkg-descr new file mode 100644 index 000000000000..24ea3cd3d8fb --- /dev/null +++ b/cad/py-verilog-parser/pkg-descr @@ -0,0 +1,3 @@ +Lark-based parser for Verilog netlists (structural Verilog without behavioral +statements). This is meant to be used to read netlists as generated by HDL logic +synthesizers such as Yosys. |